In recent years, the PCI-Express architecture has become a widely employed high-speed serial link I/O interconnect designed to transfer data between components within a computer system. PCI-Express is a serial architecture that replaces the parallel bus implementations of the PCI and PCI-X bus specification to provide platforms with greater performance, while using a much lower pin count. The PCI-Express architecture is described in the PCI-Express specifications managed and disseminated by the PCI Special Interest Group (SIG).
The PCI-Express architecture describes PCI-Express devices as having three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer, each having a transmitter and receiver portion. PCI-Express uses packets to communicate information on a serial link between components. The packets include data link layer packets (DLLPs) generated and consumed by the Data Link Layer, and transaction layer packets (TLPs) generated and consumed by the Transaction Layer. The DLLPs are used to manage the serial data link and include various types such as DLLPs related to initialization, flow control on the serial link, power management, and so forth. The TLPs are used to communicate transactions between the components, such as data read and write transactions, as well as certain types of events.
Multiple DLLPs and TLPs of different types may be scheduled for transmission at the same time. The PCI-Express Data Link Layer includes an arbiter that is in charge of prioritizing the packets for transmission. The arbiter determines which packet to transmit first based on one priority rule. In principle, the priority rule must ensure that all packets for transmission are finished within a regular time and not blocked by other types of packets. The priority rule may affect the transmission performance on a PCI-Express link. For example, assume a scheduled Ack DLLP is stalled waiting for another TLP transmission because the priority rule assigns Ack DLLPs a relatively low transmission priority, and during this time another Ack is scheduled for another received TLP. According to the PCI-Express specification, it is only necessary to transmit the second Ack DLLP, since the information the second Ack DLLP provides will supersede the information in the first Ack DLLP. That is, the Ack DLLPs are “collapsed” into a single Ack DLLP, which is an efficient use of bandwidth. On the other hand, if the priority rule assigns the highest priority to Ack DLLP transmissions, the Ack DLLP will transmit every time for every received TLP, which forfeits the potential benefit of collapsing the Ack DLLPs, which may waste transmission bandwidth. This example provides an illustration of the fact that the one priority rule may affect transmission performance.
The PCI-Express Base Specification Rev. 1.1 specifies a recommended priority rule of scheduled transmissions, shown here:                1. Completion of any transmission (TLP or DLLP) currently in progress (highest priority)        2. Nak DLLP transmissions        3. Ack DLLP transmissions scheduled for transmission as soon as possible due to receipt of a duplicated TLP-OR-expiration of the Ack latency timer        4. Flow Control DLLP transmissions (updateFC)        5. Retry Buffer re-transmissions        6. TLPs from the Transaction Layer        7. Flow Control DLLP transmissions (initFC1 and initFC2)        8. All other DLLP transmissions (lowest priority)        
The recommended priority rule specified in the PCI-Express Base Specification lacks flexibility when a root complex (RC) is involved in more complicated transaction behavior and the recommended priority rule may result in lower performance in some circumstances.